1. Field of Invention
The present invention relates to a semiconductor device, and more particularly, to a vertical transistor.
2. Description of Related Art
In order to accelerate operating speed of integrated circuit and to meet customers' demands on miniaturizing electronic devices, physical dimensions of transistors in a semiconductor device are continuously reduced. However, as the dimension of the transistor is reduced, its channel length will also decrease with ease leading to problems such as short channel effect and decrease in turn-on current. A conventional solution to said issue is to enhance the dopant concentration in the channel region. Nevertheless, this method causes an increase in a leakage current and therefore affects the reliability of devices.
Hence, to resolve said issue, the conventional horizontal transistor structure is recently replaced by a vertical transistor structure in the industry. For example, the vertical transistor structure is formed in a deep trench of the substrate. Hence, the operating speed and integration level of integrated circuits are enhanced and problems such as short channel effect are avoided. Currently, improvements in structural design and channel control of the existing vertical transistors are studied aggressively in this field.
For example, for a dynamic random access memory (DRAM), to increase the memory density means to shorten the distance between each DRAM cell. This, however, may increase parasitic capacitance between word lines and bit lines, and cause RC delay of the DRAM cells. Further, a common issue of the vertical transistor device is the floating body effect which usually results in loss of information from the memory cells. Besides, a conventional method for manufacturing a vertical DRAM, in which a surround gate surrounding the side walls of a vertical silicon column is formed, requires a complex manufacturing process. All issues described above may lead to the increase of the cost or the decrease of the device performance.